gipu/assembler/assembler.py

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import sys
import re
import struct
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import IPython
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import copy
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class AssemblerException(Exception):
pass
class InvalidRegister(AssemblerException):
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def __init__(self, register):
super().__init__("Invalid register: {}".format(register))
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class InvalidOperation(AssemblerException):
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def __init__(self, operation):
super().__init__("Invalid operation: {}".format(operation))
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class ExpectedImmediate(AssemblerException):
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def __init__(self, value):
super().__init__("Expected immediate, got {}".format(value))
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class ExpectedRegister(AssemblerException):
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def __init__(self, value):
super().__init__("Expected register, got {}".format(value))
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class IPOverwrite(AssemblerException):
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def __init__(self, instruction=None):
if instruction:
super().__init__("IP can't be overwritten. Instruction: {}".format(instruction))
else:
super().__init__("IP can't be overwritten.")
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class InvalidValue(AssemblerException):
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def __init__(self, instruction):
super().__init__("Invalid value while assembling: {}".format(instruction))
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class VMAssembler:
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def __init__(self, key, data):
self.data = data
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self.assembled_code = bytearray()
self.functions = []
self.decrypt_ops(key)
self.parse_functions()
main = next((x for x in self.functions if x.name == "main"), None)
if main == None:
print("Main has to be defined")
return
def parse_functions(self):
cur_fun_size = 0
cur_fun_name = None
fun_start = 0
# first parse to get every function name
for i, line in enumerate(self.data):
match = function_re.match(line)
if match:
if cur_fun_name:
f = VMFunction(cur_fun_name, self.data[fun_start:i])
self.functions.append(f)
cur_fun_name = match.group(1)
fun_start = i + 1
f = VMFunction(cur_fun_name, self.data[fun_start:i + 1])
self.functions.append(f)
# putting main in first position in order to assemble it first
for i, f in enumerate(self.functions):
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if f.name == "main" and i is not 0:
self.functions[0], self.functions[
i] = self.functions[i], self.functions[0]
break
# calculating functions offsets
for i in range(1, len(self.functions)):
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prev_fun_tot_size = self.functions[
i - 1].size + self.functions[i - 1].offset
cur_fun_size = self.functions[i].size
self.functions[i].set_offset(prev_fun_tot_size)
return
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def parse(self):
for f in self.functions:
for i in f.instructions:
action = getattr(self, "{}".format(i.opcode.method))
action(i)
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def imm2reg(self, instruction):
"""
Intel syntax -> REG, IMM
"""
opcode = instruction.opcode
reg = instruction.args[0]
imm = instruction.args[1]
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if reg.name == "ip":
raise IPOverwrite(instruction)
if not imm.isimm():
raise ExpectedImmediate(imm)
if not reg.isreg():
raise ExpectedRegister(reg)
if not opcode.uint8() or not reg.uint8() or not imm.uint16():
raise InvalidValue(instruction)
self.assembled_code += opcode.uint8() + reg.uint8() + imm.uint16()
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return
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def reg2reg(self, instruction):
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"""
Intel syntax -> DST_REG, SRC_REG
"""
opcode = instruction.opcode
dst_reg = instruction.args[0]
src_reg = instruction.args[1]
if dst_reg.name == "ip" or src_reg.name == "ip":
raise IPOverwrite(instruction)
if not dst_reg.isreg():
raise ExpectedRegister(dst_reg)
if not src_reg.isreg():
raise ExpectedRegister(src_reg)
if not opcode.uint8() or not dst_reg.uint8() or not src_reg.uint8():
raise InvalidValue(instruction)
byte_with_nibbles = struct.pack("<B", dst_reg.uint8()[0] << 4 ^ (
src_reg.uint8()[0] & 0b00001111))
self.assembled_code += opcode.uint8() + byte_with_nibbles
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return
def reg2imm(self, instruction):
"""
Intel syntax -> IMM, REG
"""
opcode = instruction.opcode
imm = instruction.args[0]
reg = instruction.args[1]
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if reg.name == "ip":
raise IPOverwrite(instruction)
if not imm.isimm():
raise ExpectedImmediate(imm)
if not reg.isreg():
raise ExpectedRegister(reg)
if not opcode.uint8() or not reg.uint8() or not imm.uint16():
raise InvalidValue(instruction)
self.assembled_code += opcode.uint8() + imm.uint16() + reg.uint8()
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return
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def byt2reg(self, instruction):
"""
Intel syntax -> REG, [BYTE]IMM
"""
opcode = instruction.opcode
reg = instruction.args[0]
imm = instruction.args[1]
if reg.name == "ip":
raise IPOverwrite(instruction)
if not imm.isimm():
raise ExpectedImmediate(imm)
if not reg.isreg():
raise ExpectedRegister(reg)
if not opcode.uint8() or not reg.uint8() or not imm.uint8():
raise InvalidValue(instruction)
self.assembled_code += opcode.uint8() + reg.uint8() + imm.uint8()
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return
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def regonly(self, instruction):
"""
Instruction with only an argument: a register
"""
opcode = instruction.opcode
reg = instruction.args[0]
if reg.name == "ip":
raise IPOverwrite(instruction)
if not reg.isreg():
raise ExpectedRegister(reg)
if not opcode.uint8() or not reg.uint8():
raise InvalidValue(instruction)
self.assembled_code += opcode.uint8() + reg.uint8()
return
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def immonly(self, instruction):
"""
Instruction with only an argument: an immediate
"""
opcode = instruction.opcode
imm = instruction.args[0]
if not imm.isimm():
raise ExpectedImmediate(imm)
if not opcode.uint8() or not imm.uint16():
raise InvalidValue(instruction)
self.assembled_code += opcode.uint8() + imm.uint16()
return
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def jump(self, instruction):
imm_op_re = re.compile(".*[iI]$")
reg_op_re = re.compile(".*[rR]$")
symcall = symcall_re.match(str(instruction))
dst = instruction.args[0]
# let's check if the jump is to a label or a function
if symcall:
# the symbal has not been resolved
if dst.name == dst.value:
# check whether it is a function
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val = next(
(x.offset for x in self.functions if x.name == dst.name), None)
# check whether it is a label
if val == None:
for f in self.functions:
for i in f.instructions:
if i.label == dst.name:
val = f.offset_of_label(dst) + f.offset
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if val == None:
raise AssemblerException()
# resolving the symbol
instruction.args[0].set_value(val)
# define the kind of jump: to immediate or to register
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if imm_op_re.match(instruction.opcode.name):
self.immonly(instruction)
elif reg_op_re.match(instruction.opcode.name):
self.regonly(instruction)
else:
raise AssemblerException()
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def single(self, instruction):
"""
Instruction with no arguments
"""
opcode = instruction.opcode
self.assembled_code += opcode.uint8()
return
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def decrypt_ops(self, key):
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key_ba = bytearray(key, 'utf-8')
olds = copy.deepcopy(ops)
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# RC4 KSA! :-P
arr = [i for i in range(256)]
j = 0
for i in range(len(arr)):
j = (j + arr[i] + key_ba[i % len(key)]) % len(arr)
arr[i], arr[j] = arr[j], arr[i]
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for i, o in enumerate(ops):
o.set_value(arr[i])
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for o, n in zip(olds, ops):
print("{} : {}->{}".format(o.name, hex(o.value), hex(n.value)))
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class VMFunction:
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def __init__(self, name, code):
self.name = name
self.size = 0
self.offset = 0
self.instructions = []
# populating instructions
i = 0
while i < len(code):
line = code[i]
ins = instruction_re.match(line)
label = label_re.match(line)
if label:
label_name = label.group(1)
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self.instructions.append(
VMInstruction(code[i + 1], label_name))
i += 2
elif ins:
self.instructions.append(VMInstruction(line))
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i += 1
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else:
raise InvalidOperation(line)
self.calc_size()
def calc_size(self):
for i in self.instructions:
self.size += i.size
def set_offset(self, offset):
self.offset = offset
def offset_of_label(self, label):
offset = 0
for i in self.instructions:
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if str(i.label) == str(label):
break
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offset += i.size
return offset
def __repr__(self):
return "{}: size {}, offset {}".format(self.name, hex(self.size), hex(self.offset))
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class VMInstruction:
"""
Represents an instruction the VM recognizes.
e.g: MOVI [R0, 2]
^ ^
opcode args
"""
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def __init__(self, line, label=None):
self.opcode = None
self.args = []
self.size = 1
self.label = label
ins = instruction_re.match(line)
symcall = symcall_re.match(line)
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opcode = ins.group(1)
self.opcode = next((x for x in ops if x.name == opcode), None)
if self.opcode == None:
raise InvalidOperation(opcode)
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args = [x for x in ins.groups()[1:] if x is not None]
for a in args:
if immediate_re.match(a) or symcall:
# directly append the immediate
self.args.append(VMComponent(a, a))
self.size += 2
continue
elif register_re.match(a):
# create a VM component for a register
reg = next((x for x in regs if x.name == a), None)
if reg == None:
raise InvalidRegister(a)
self.args.append(reg)
self.size += 1
continue
def __repr__(self):
return "{} {}".format(self.opcode.name, ", ".join([x.name for x in self.args]))
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class VMComponent:
"""
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Represents a register, operation or an immediate the VM recognizes
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"""
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def __init__(self, name, value, method=None):
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self.name = name.casefold()
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self.value = value
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self.method = method
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def __repr__(self):
return "{}".format(self.name)
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def set_name(self, name):
self.name = name
def set_value(self, value):
self.value = value
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def uint8(self):
numre = re.compile("^[0-9]+$")
if isinstance(self.value, int):
return struct.pack("<B", self.value)
elif self.value.startswith("0x"):
return struct.pack("<B", int(self.value, 16))
elif numre.match(self.value): # only numbers
return struct.pack("<B", int(self.value))
return None
def uint16(self):
numre = re.compile("^[0-9]+$")
if isinstance(self.value, int):
return struct.pack("<H", self.value)
elif self.value.startswith("0x"):
return struct.pack("<H", int(self.value, 16))
elif numre.match(self.value): # only numbers
return struct.pack("<H", int(self.value))
return None
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def isreg(self):
if self.name not in [x.casefold() for x in reg_names]:
return False
return True
def isop(self):
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if self.name not in [x[0].casefold() for x in op_names]:
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return False
return True
def isimm(self):
name_alpha = alpha_re.match(str(self.name))
value_alpha = alpha_re.match(str(self.value))
name_imm = immediate_re.match(str(self.name))
value_imm = immediate_re.match(str(self.value))
if name_alpha and value_alpha and not name_imm and not value_imm:
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return False
return True
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op_names = [["MOVI", "imm2reg"],
["MOVR", "reg2reg"],
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["LODI", "imm2reg"],
["LODR", "reg2reg"],
["STRI", "imm2reg"],
["STRR", "reg2reg"],
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["ADDI", "imm2reg"],
["ADDR", "reg2reg"],
["SUBI", "imm2reg"],
["SUBR", "reg2reg"],
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["ANDB", "byt2reg"],
["ANDW", "imm2reg"],
["ANDR", "reg2reg"],
["YORB", "byt2reg"],
["YORW", "imm2reg"],
["YORR", "reg2reg"],
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["XORB", "byt2reg"],
["XORW", "imm2reg"],
["XORR", "reg2reg"],
["NOTR", "regonly"],
["MULI", "imm2reg"],
["MULR", "reg2reg"],
["DIVI", "imm2reg"],
["DIVR", "reg2reg"],
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["SHLI", "imm2reg"],
["SHLR", "reg2reg"],
["SHRI", "imm2reg"],
["SHRR", "reg2reg"],
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["PUSH", "regonly"],
["POOP", "regonly"],
["CMPI", "imm2reg"],
["CMPR", "reg2reg"],
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["JMPI", "jump"],
["JMPR", "jump"],
["JPAI", "jump"],
["JPAR", "jump"],
["JPBI", "jump"],
["JPBR", "jump"],
["JPEI", "jump"],
["JPER", "jump"],
["JPNI", "jump"],
["JPNR", "jump"],
["RETN", "single"],
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["SHIT", "single"],
["NOPE", "single"],
["GRMN", "single"]]
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reg_names = ["R0", "R1", "R2", "R3", "S0", "S1", "S2", "S3", "IP", "BP", "SP"]
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ops = [VMComponent(le[0], i, le[1]) for i, le in enumerate(op_names)]
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regs = [VMComponent(s.casefold(), i) for i, s in enumerate(reg_names)]
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instruction_re = re.compile(
"^([\w]{4})(?:\ +(?:([\w]+)\ *(?:,[\ ]*([\w]+))*))?$") # 1: opcode 2+: args
function_re = re.compile("(?:def\ )([a-zA-Z]*)\:")
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immediate_re = re.compile("(?:0x)?[0-9a-fA-F]+$")
alpha_re = re.compile("^[a-zA-Z]*$")
register_re = re.compile("(^[rRsS][0-4]$)|([iIrRsS][pP]$)")
label_re = re.compile("^([a-zA-Z]+)\:$")
symcall_re = re.compile("^([jJ][pPmM][pPaAbBeEnN][iIrR])\ +([\w]*)$")
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def main():
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if len(sys.argv) < 4:
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print("Usage: {} opcodes_key file_to_assemble output".format(
sys.argv[0]))
return
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with open(sys.argv[2], 'r') as f:
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filedata = f.readlines()
filedata = [x.strip() for x in filedata if x.strip()]
vma = VMAssembler(sys.argv[1], filedata)
vma.parse()
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with open(sys.argv[3], 'wb') as f:
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f.write(vma.assembled_code)
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if __name__ == '__main__':
main()