gipu/python/assembler.py

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Python
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import sys
import re
import struct
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import IPython
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class InvalidRegisterException(Exception):
def __init__(self, register):
super().__init__("Invalid register: {}".format(register))
class InvalidOperationException(Exception):
def __init__(self, operation):
super().__init__("Invalid operation: {}".format(operation))
class ExpectedImmediateException(Exception):
def __init__(self, value):
super().__init__("Expected immediate, got {}".format(value))
class ExpectedRegisterException(Exception):
def __init__(self, value):
super().__init__("Expected register, got {}".format(value))
class IPOverwriteException(Exception):
def __init__(self, instruction=None):
if instruction:
super().__init__("IP can't be overwritten. Instruction: {}".format(instruction))
else:
super().__init__("IP can't be overwritten.")
class InvalidValueException(Exception):
def __init__(self, instruction):
super().__init__("Invalid value while assembling: {}".format(instruction))
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class VMAssembler:
assembled_code = bytearray()
def parse(self, instruction):
action = getattr(self, "{}".format(instruction.opcode.name))
action(instruction)
def process_code_line(self, line):
sys.stdout.write("CODE: ")
components = [x for x in re.split('\W', line) if x]
instruction = VMInstruction(components[0], components[1:])
self.parse(instruction)
def imm2reg(self, instruction):
"""
Intel syntax -> REG, IMM
"""
opcode = instruction.opcode
reg = instruction.args[0]
imm = instruction.args[1]
print(instruction)
if reg.name != "ip":
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if imm.isimm():
if reg.isreg():
if opcode.uint8() and reg.uint8() and imm.uint16():
self.assembled_code += opcode.uint8() + reg.uint8() + imm.uint16()
else:
raise InvalidValueException(instruction)
else:
raise ExpectedRegisterException(reg)
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else:
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raise ExpectedImmediateException(imm)
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else:
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raise IPOverwriteException(instruction)
return
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def reg2reg(self, instruction):
return
def reg2imm(self, instruction):
"""
Intel syntax -> IMM, REG
"""
opcode = instruction.opcode
imm = instruction.args[0]
reg = instruction.args[1]
print(instruction)
if reg.name != "ip":
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if imm.isimm():
if reg.isreg():
if opcode.uint8() and reg.uint8() and imm.uint16():
self.assembled_code += opcode.uint8() + imm.uint16() + reg.uint8()
else:
raise InvalidValueException(instruction)
else:
raise ExpectedRegisterException(reg)
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else:
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raise ExpectedImmediateException(imm)
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else:
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raise IPOverwriteException(instruction)
return
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def imm(self, instruction):
return
def movi(self, instruction):
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self.imm2reg(instruction)
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def movr(self, instruction):
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self.reg2reg(instruction)
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def getm(self, instruction):
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self.imm2reg(instruction)
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def putm(self, instruction):
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self.reg2imm(instruction)
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def addi(self, instruction):
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self.imm2reg(instruction)
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class VMComponent:
"""
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Represents a register, operation or an immediate the VM recognizes
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"""
name = ""
value = ""
def __init__(self, name, value):
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self.name = name.casefold()
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self.value = value
def __repr__(self):
return "{}".format(self.name)
def uint8(self):
numre = re.compile("^[0-9]+$")
if isinstance(self.value, int):
return struct.pack("<B", self.value)
elif self.value.startswith("0x"):
return struct.pack("<B", int(self.value, 16))
elif numre.match(self.value): # only numbers
return struct.pack("<B", int(self.value))
return None
def uint16(self):
numre = re.compile("^[0-9]+$")
if isinstance(self.value, int):
return struct.pack("<H", self.value)
elif self.value.startswith("0x"):
return struct.pack("<H", int(self.value, 16))
elif numre.match(self.value): # only numbers
return struct.pack("<H", int(self.value))
return None
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def isreg(self):
if self.name not in [x.casefold() for x in reg_names]:
return False
return True
def isop(self):
if self.name not in [x.casefold() for x in op_names]:
return False
return True
def isimm(self):
if self.name != self.value:
return False
return True
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class VMInstruction:
"""
Represents an instruction the VM recognizes.
e.g: MOVI [R0, 2]
^ ^
opcode args
"""
def __init__(self, opcode, instr_list):
# TODO EXCEPTION SE REGISTRO / IMM / OPCODE NON VALIDO
immediate_regexp = re.compile("^(0x*|[0-9]*$)")
opc_name, opc_value = value_from_list(ops, opcode)
self.opcode = VMComponent(opc_name, opc_value)
self.args = []
for el in instr_list:
if not immediate_regexp.match(el):
# create a VM component for a register
reg_name, reg_value = value_from_list(regs, el)
self.args.append(VMComponent(reg_name, reg_value))
else:
# directly append the immediate
self.args.append(VMComponent(el, el))
def __repr__(self):
return "{} {}".format(self.opcode.name, ", ".join([x.name for x in self.args]))
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op_names = ["MOVI",
"MOVR",
"GETM",
"PUTM",
"ADDI",
"ADDR",
"SUBI",
"SUBR",
"XORI",
"XORR",
"NOTI",
"NOTR",
"MULI",
"MULR",
"DIVI",
"DIVR",
"PUSH",
"POOP",
"CALL",
"HALT",
"NOPE"]
reg_names = ["R0", "R1", "R2", "R3", "S0", "S1", "S2", "S3", "IP", "BP", "SP"]
section_names = ["DATA:", "CODE:", "STACK:"]
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section_flags = {s.casefold(): i + 1 for i, s in enumerate(section_names)}
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ops = [VMComponent(s.casefold(), i) for i, s in enumerate(op_names)]
regs = [VMComponent(s.casefold(), i) for i, s in enumerate(reg_names)]
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def value_from_list(fromlist, name):
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global ops, regs
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"""
returns a tuple (name, value) from a list of VMComponents
"""
for el in fromlist:
if el.name == name:
return (el.name, el.value)
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if fromlist == ops:
raise InvalidOperationException(name)
elif fromlist == regs:
raise InvalidRegisterException(name)
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def name_from_list(fromlist, value):
"""
returns a tuple (name, value) from a list of VMComponents
"""
for el in fromlist:
if el.value == value:
return (el.name, el.value)
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return None
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def assemble_data(line):
sys.stdout.write("DATA:\t")
sys.stdout.write(line.strip(",") + "\n")
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def main():
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if len(sys.argv) < 3:
print("Usage: {} file_to_assemble output".format(sys.argv[0]))
return
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vma = VMAssembler()
with open(sys.argv[1], 'r') as f:
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gen = (line.casefold().strip("\n") for line in f if line != "\n")
flag = None
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for line in gen:
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if line in section_flags:
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flag = section_flags[line]
continue
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if flag == section_flags["data:"]:
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vma.process_code_line(line)
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elif flag == section_flags["code:"]:
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vma.process_code_line(line)
if not flag:
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sys.stderr.write(
"Nothing was assembled! Did you use the section delimiters?\n")
with open(sys.argv[2], 'wb') as f:
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f.write(vma.assembled_code)
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if __name__ == '__main__':
main()