354 lines
11 KiB
Python
354 lines
11 KiB
Python
import sys
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import re
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import struct
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import IPython
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import copy
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class AssemblerException(Exception):
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pass
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class InvalidRegister(AssemblerException):
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def __init__(self, register):
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super().__init__("Invalid register: {}".format(register))
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class InvalidOperation(AssemblerException):
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def __init__(self, operation):
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super().__init__("Invalid operation: {}".format(operation))
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class ExpectedImmediate(AssemblerException):
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def __init__(self, value):
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super().__init__("Expected immediate, got {}".format(value))
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class ExpectedRegister(AssemblerException):
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def __init__(self, value):
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super().__init__("Expected register, got {}".format(value))
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class IPOverwrite(AssemblerException):
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def __init__(self, instruction=None):
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if instruction:
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super().__init__("IP can't be overwritten. Instruction: {}".format(instruction))
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else:
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super().__init__("IP can't be overwritten.")
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class InvalidValue(AssemblerException):
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def __init__(self, instruction):
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super().__init__("Invalid value while assembling: {}".format(instruction))
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rol = lambda val, r_bits, max_bits: \
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(val << r_bits % max_bits) & (2**max_bits - 1) | \
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((val & (2**max_bits - 1)) >> (max_bits - (r_bits % max_bits)))
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class VMAssembler:
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def __init__(self, key):
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self.assembled_code = bytearray()
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self.define_ops(key)
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def parse(self, instruction):
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action = getattr(self, "{}".format(instruction.opcode.method))
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action(instruction)
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def process_code_line(self, line):
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sys.stdout.write("CODE: ")
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components = [x for x in re.split('\W', line) if x]
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instruction = VMInstruction(components[0], components[1:])
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sys.stdout.write(str(instruction) + "\n")
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self.parse(instruction)
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def imm2reg(self, instruction):
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"""
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Intel syntax -> REG, IMM
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"""
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opcode = instruction.opcode
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reg = instruction.args[0]
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imm = instruction.args[1]
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if reg.name == "ip":
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raise IPOverwrite(instruction)
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if not imm.isimm():
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raise ExpectedImmediate(imm)
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if not reg.isreg():
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raise ExpectedRegister(reg)
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if not opcode.uint8() or not reg.uint8() or not imm.uint16():
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raise InvalidValue(instruction)
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self.assembled_code += opcode.uint8() + reg.uint8() + imm.uint16()
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return
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def reg2reg(self, instruction):
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"""
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Intel syntax -> DST_REG, SRC_REG
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"""
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opcode = instruction.opcode
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dst_reg = instruction.args[0]
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src_reg = instruction.args[1]
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if dst_reg.name == "ip" or src_reg.name == "ip":
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raise IPOverwrite(instruction)
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if not dst_reg.isreg():
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raise ExpectedRegister(dst_reg)
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if not src_reg.isreg():
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raise ExpectedRegister(src_reg)
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if not opcode.uint8() or not dst_reg.uint8() or not src_reg.uint8():
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raise InvalidValue(instruction)
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byte_with_nibbles = struct.pack("<B", dst_reg.uint8()[0] << 4 ^ (
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src_reg.uint8()[0] & 0b00001111))
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self.assembled_code += opcode.uint8() + byte_with_nibbles
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return
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def reg2imm(self, instruction):
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"""
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Intel syntax -> IMM, REG
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"""
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opcode = instruction.opcode
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imm = instruction.args[0]
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reg = instruction.args[1]
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if reg.name == "ip":
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raise IPOverwrite(instruction)
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if not imm.isimm():
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raise ExpectedImmediate(imm)
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if not reg.isreg():
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raise ExpectedRegister(reg)
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if not opcode.uint8() or not reg.uint8() or not imm.uint16():
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raise InvalidValue(instruction)
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self.assembled_code += opcode.uint8() + imm.uint16() + reg.uint8()
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return
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def byt2reg(self, instruction):
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"""
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Intel syntax -> REG, [BYTE]IMM
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"""
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opcode = instruction.opcode
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reg = instruction.args[0]
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imm = instruction.args[1]
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if reg.name == "ip":
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raise IPOverwrite(instruction)
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if not imm.isimm():
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raise ExpectedImmediate(imm)
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if not reg.isreg():
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raise ExpectedRegister(reg)
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if not opcode.uint8() or not reg.uint8() or not imm.uint8():
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raise InvalidValue(instruction)
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self.assembled_code += opcode.uint8() + reg.uint8() + imm.uint8()
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return
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def regonly(self, instruction):
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"""
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Instruction with only an argument: a register
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"""
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opcode = instruction.opcode
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reg = instruction.args[0]
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if reg.name == "ip":
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raise IPOverwrite(instruction)
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if not reg.isreg():
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raise ExpectedRegister(reg)
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if not opcode.uint8() or not reg.uint8():
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raise InvalidValue(instruction)
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self.assembled_code += opcode.uint8() + reg.uint8()
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return
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def immonly(self, instruction):
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"""
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Instruction with only an argument: an immediate
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"""
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opcode = instruction.opcode
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imm = instruction.args[0]
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if not imm.isimm():
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raise ExpectedImmediate(imm)
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if not opcode.uint8() or not imm.uint16():
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raise InvalidValue(instruction)
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self.assembled_code += opcode.uint8() + imm.uint16()
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return
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def single(self, instruction):
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"""
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Instruction with no arguments
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"""
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opcode = instruction.opcode
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self.assembled_code += opcode.uint8()
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return
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def define_ops(self, key):
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key_ba = bytearray(key, 'utf-8')
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olds = copy.deepcopy(ops)
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for b in key_ba:
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for op_com in ops:
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op_com.set_value(rol(b ^ op_com.value, b % 8, 8))
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for i in ops:
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for j in ops:
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j.set_value(rol(j.value, i.value % 8, 8))
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for o, n in zip(olds, ops):
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print("{} : {}->{}".format(o.name, hex(o.value), hex(n.value)))
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class VMComponent:
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"""
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Represents a register, operation or an immediate the VM recognizes
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"""
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def __init__(self, name, value, method=None):
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self.name = name.casefold()
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self.value = value
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self.method = method
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def __repr__(self):
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return "{}".format(self.name)
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def set_name(self, name):
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self.name = name
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def set_value(self, value):
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self.value = value
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def uint8(self):
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numre = re.compile("^[0-9]+$")
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if isinstance(self.value, int):
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return struct.pack("<B", self.value)
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elif self.value.startswith("0x"):
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return struct.pack("<B", int(self.value, 16))
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elif numre.match(self.value): # only numbers
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return struct.pack("<B", int(self.value))
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return None
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def uint16(self):
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numre = re.compile("^[0-9]+$")
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if isinstance(self.value, int):
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return struct.pack("<H", self.value)
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elif self.value.startswith("0x"):
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return struct.pack("<H", int(self.value, 16))
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elif numre.match(self.value): # only numbers
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return struct.pack("<H", int(self.value))
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return None
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def isreg(self):
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if self.name not in [x.casefold() for x in reg_names]:
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return False
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return True
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def isop(self):
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if self.name not in [x[0].casefold() for x in op_names]:
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return False
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return True
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def isimm(self):
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if self.name != self.value:
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return False
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return True
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class VMInstruction:
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"""
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Represents an instruction the VM recognizes.
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e.g: MOVI [R0, 2]
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^ ^
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opcode args
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"""
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def __init__(self, opcode, instr_list):
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immediate_regexp = re.compile("^(0x*|[0-9]*$)")
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self.opcode = next((x for x in ops if x.name == opcode), None)
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if self.opcode == None:
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raise InvalidOperation(opcode)
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self.args = []
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for el in instr_list:
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if not immediate_regexp.match(el):
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# create a VM component for a register
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reg_comp = next((x for x in regs if x.name == el), None)
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self.args.append(reg_comp)
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else:
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# directly append the immediate
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self.args.append(VMComponent(el, el))
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def __repr__(self):
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return "{} {}".format(self.opcode.name, ", ".join([x.name for x in self.args]))
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op_names = [["MOVI", "imm2reg"],
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["MOVR", "reg2reg"],
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["LOAD", "imm2reg"],
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["STOR", "reg2imm"],
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["ADDI", "imm2reg"],
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["ADDR", "reg2reg"],
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["SUBI", "imm2reg"],
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["SUBR", "reg2reg"],
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["ANDB", "byt2reg"],
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["ANDW", "imm2reg"],
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["ANDR", "reg2reg"],
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["YORB", "byt2reg"],
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["YORW", "imm2reg"],
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["YORR", "reg2reg"],
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["XORB", "byt2reg"],
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["XORW", "imm2reg"],
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["XORR", "reg2reg"],
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["NOTR", "regonly"],
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["MULI", "imm2reg"],
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["MULR", "reg2reg"],
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["DIVI", "imm2reg"],
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["DIVR", "reg2reg"],
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["PUSH", "regonly"],
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["POOP", "regonly"],
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["CMPI", "imm2reg"],
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["CMPR", "reg2reg"],
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["JMPI", "immonly"],
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["JMPR", "regonly"],
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["JPAI", "immonly"],
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["JPAR", "regonly"],
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["JPBI", "immonly"],
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["JPBR", "regonly"],
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["JPEI", "immonly"],
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["JPER", "regonly"],
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["JPNI", "immonly"],
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["JPNR", "regonly"],
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["SHIT", "single"],
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["NOPE", "single"],
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["GRMN", "single"]]
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reg_names = ["R0", "R1", "R2", "R3", "S0", "S1", "S2", "S3", "IP", "BP", "SP"]
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section_names = ["DATA:", "CODE:", "STACK:"]
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section_flags = {s.casefold(): i + 1 for i, s in enumerate(section_names)}
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ops = [VMComponent(le[0], i, le[1]) for i, le in enumerate(op_names)]
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regs = [VMComponent(s.casefold(), i) for i, s in enumerate(reg_names)]
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def assemble_data(line):
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sys.stdout.write("DATA:\t")
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sys.stdout.write(line.strip(",") + "\n")
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def main():
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if len(sys.argv) < 4:
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print("Usage: {} opcodes_key file_to_assemble output".format(
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sys.argv[0]))
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return
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vma = VMAssembler(sys.argv[1])
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with open(sys.argv[2], 'r') as f:
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gen = (line.casefold().strip() for line in f if line != "\n")
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flag = None
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for line in gen:
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if line in section_flags:
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flag = section_flags[line]
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continue
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if flag == section_flags["data:"]:
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vma.process_code_line(line)
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elif flag == section_flags["code:"]:
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vma.process_code_line(line)
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if not flag:
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sys.stderr.write(
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"Nothing was assembled! Did you use the section delimiters?\n")
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with open(sys.argv[3], 'wb') as f:
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f.write(vma.assembled_code)
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if __name__ == '__main__':
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main()
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