LODI, LODR, STRI, STRR
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0dfd9bdb57
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@ -6,7 +6,8 @@
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void encrypt(uint32_t *v, uint32_t *k) {
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uint32_t v0 = v[0], v1 = v[1], sum = 0, i; /* set up */
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uint32_t delta = 0x9e3779b9; /* a key schedule constant */
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//uint32_t delta = 0x9e3779b9; /* a key schedule constant */
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uint16_t delta= 0x9e37;
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uint32_t k0 = k[0], k1 = k[1], k2 = k[2], k3 = k[3]; /* cache key */
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for (i = 0; i < 32; i++) { /* basic cycle start */
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sum += delta;
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12
vm/opcodes.h
12
vm/opcodes.h
@ -4,8 +4,10 @@ MEMORY LOCATIONS AND IMMEDIATES ARE 16 BITS LONG
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enum OPS_STARTING_VALUES {
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MOVI,
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MOVR,
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LOAD,
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STOR,
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LODI,
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LODR,
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STRI,
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STRR,
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ADDI,
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ADDR,
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SUBI,
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@ -67,8 +69,10 @@ INSTRUCTION SIZES
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*/
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#define MOVI_SIZE IMM2REG
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#define MOVR_SIZE REG2REG
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#define LOAD_SIZE IMM2REG
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#define STOR_SIZE REG2IMM
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#define LODI_SIZE IMM2REG
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#define LODR_SIZE REG2REG
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#define STRI_SIZE IMM2REG
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#define STRR_SIZE REG2REG
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#define ADDI_SIZE IMM2REG
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#define ADDR_SIZE REG2REG
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#define SUBI_SIZE IMM2REG
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56
vm/vm.cpp
56
vm/vm.cpp
@ -201,32 +201,58 @@ bool VM::execMOVR(void) {
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return true;
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}
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bool VM::execLOAD(void) {
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bool VM::execLODI(void) {
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/*
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LOAD R0, 0x1000 -> R0 = data[0x1000]
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LODI R0, 0x1000 -> R0 = data[0x1000]
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*/
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uint8_t dst;
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uint16_t src;
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dst = as.code[regs[IP] + 1];
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src = *((uint16_t *)&as.code[regs[IP] + 2]);
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DBG_INFO(("LOAD %s, 0x%x\n", getRegName(dst), src));
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DBG_INFO(("LODI %s, 0x%x\n", getRegName(dst), src));
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regs[dst] = *((uint16_t *)&as.data[src]);
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return true;
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}
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bool VM::execSTOR(void) {
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bool VM::execLODR(void) {
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/*
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STOR 0x1000, R0 -> data[0x1000] = R0
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LODR R1, R0 -> R1 = data[R0]
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*/
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uint16_t dst;
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uint8_t src;
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dst = as.code[regs[IP] + 1] >> 4;
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src = as.code[regs[IP] + 1] & 0b00001111;
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DBG_INFO(("LODR %s, %s\n", getRegName(dst), getRegName(src)));
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regs[dst] = *((uint16_t *)&as.data[regs[src]]);
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return true;
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}
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bool VM::execSTRI(void) {
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/*
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STRI 0x1000, R0 -> data[0x1000] = R0
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*/
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uint16_t dst;
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uint8_t src;
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dst = *((uint16_t *)&as.code[regs[IP] + 1]);
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src = as.code[regs[IP] + 3];
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DBG_INFO(("STOR 0x%x, %s\n", dst, getRegName(src)));
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DBG_INFO(("STRI 0x%x, %s\n", dst, getRegName(src)));
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*((uint16_t *)&as.data[dst]) = regs[src];
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return true;
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}
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bool VM::execSTRR(void) {
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/*
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STRR R1, R0 -> data[R1] = R0
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*/
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uint8_t dst;
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uint8_t src;
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dst = as.code[regs[IP] + 1] >> 4;
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src = as.code[regs[IP] + 1] & 0b00001111;
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DBG_INFO(("STRR %s, %s\n", getRegName(dst), getRegName(src)));
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*((uint16_t *)&as.data[regs[dst]]) = regs[src];
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return true;
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}
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bool VM::execADDI(void) {
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/*
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ADDI R0, 0x2 -> R0 += 2
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@ -750,12 +776,18 @@ void VM::run(void) {
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} else if (opcode == OPS[MOVR]) {
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execMOVR();
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regs[IP] += MOVR_SIZE;
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} else if (opcode == OPS[LOAD]) {
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execLOAD();
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regs[IP] += LOAD_SIZE;
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} else if (opcode == OPS[STOR]) {
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execSTOR();
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regs[IP] += STOR_SIZE;
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} else if (opcode == OPS[LODI]) {
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execLODI();
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regs[IP] += LODI_SIZE;
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} else if (opcode == OPS[LODR]) {
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execLODR();
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regs[IP] += LODR_SIZE;
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} else if (opcode == OPS[STRI]) {
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execSTRI();
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regs[IP] += STRI_SIZE;
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} else if (opcode == OPS[STRR]) {
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execSTRR();
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regs[IP] += STRR_SIZE;
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} else if (opcode == OPS[ADDI]) {
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execADDI();
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regs[IP] += ADDI_SIZE;
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