diff --git a/assembler/assembler.py b/assembler/assembler.py index 10e6b7a..abf574b 100644 --- a/assembler/assembler.py +++ b/assembler/assembler.py @@ -102,6 +102,7 @@ class VMAssembler: """ Intel syntax -> REG, IMM """ + print(instruction.args) opcode = instruction.opcode reg = instruction.args[0] imm = instruction.args[1] @@ -268,14 +269,18 @@ class VMFunction: line = code[i] ins = instruction_re.match(line) label = label_re.match(line) + print(line) if label: label_name = label.group(1) + print("APPENDING {} TO {}".format(code[i], self.name)) self.instructions.append(VMInstruction(code[i+1], label_name)) i += 2 elif ins: + print("APPENDING {} TO {}".format(code[i], self.name)) self.instructions.append(VMInstruction(line)) + else: + raise InvalidOperation(line) i+=1 - self.calc_size() def calc_size(self): @@ -317,9 +322,11 @@ class VMInstruction: self.opcode = next((x for x in ops if x.name == opcode), None) if self.opcode == None: raise InvalidOperation(opcode) - + args = [x for x in ins.groups()[1:] if x is not None] + print(args) for a in args: + print(a) if immediate_re.match(a) or symcall: # directly append the immediate self.args.append(VMComponent(a, a)) @@ -443,7 +450,7 @@ ops = [VMComponent(le[0], i, le[1]) for i, le in enumerate(op_names)] regs = [VMComponent(s.casefold(), i) for i, s in enumerate(reg_names)] instruction_re = re.compile("^([\w]{4})(?:\ +(?:([\w]+)\ *(?:,[\ ]*([\w]+))*))?$") # 1: opcode 2+: args function_re = re.compile("(?:def\ )([a-zA-Z]*)\:") -immediate_re = re.compile("(?:0x)?[0-9]*[0-9]$") +immediate_re = re.compile("(?:0x)?[0-9a-fA-F]+$") alpha_re = re.compile("^[a-zA-Z]*$") register_re = re.compile("(^[rRsS][0-4]$)|([iIrRsS][pP]$)") label_re = re.compile("^([a-zA-Z]+)\:$")