Aggiunte a documentazione

IMPLEMENTATION.md

@@ -22,6 +22,33 @@ for i, o in enumerate(ops):
     o.set_value(arr[i])
 ```
 
+# Assembling, labels and functions
+
+The enclosed assembler recognizes **labels** and **functions**. The **main** function has to be defined. Here is an example:
+
+```
+def foo:
+addi r0, 0x3
+movi r1, 0x1
+retn
+
+def main: # main is mandatory
+movi r0, 0xff
+nope
+jmpi label # jumping to label
+nope
+addi r0, 0x2
+label: # defining a label
+grmn
+call foo
+shit
+```
+In order to jump to a label or a function, an *immediate type* jump has to be used (`JMPI, JPBI, JPAI`, etc...). The `CALL` instruction is used to save where the program has to restore its execution after a function call.
+
+The assembler puts the **main** function as first in the code section meaning its code will be located at offset 0. Every other function will follow.
+
+![Functions]
+
 # Instruction set
 The instruction set I come out wants to be "RISC"-oriented but I have to admit that it is more "CISC"-oriented *(Confusing Instruction Set Computer)*.
 Also, since I decided that every instruction had to be 4 chars long, some name adaptation may have encountered some quality issue... (yes, `POP`, I'm looking at you)
@@ -96,141 +123,141 @@ Effect: R1 is decremented by R0
 ```
 ## ANDB
 ```
-Full name:
-Usage:
-Effect: 
+Full name: AND Byte (immediate)
+Usage: ANDB R0, 0xFF
+Effect: R0's lower byte is and-ed by 0xFF.
 ```
 ## ANDW
 ```
-Full name:
-Usage:
-Effect: 
+Full name: AND Word (immediate)
+Usage: ANDW R0, 0xFFFF
+Effect: R0's is and-ed by 0xFFFF.
 ```
 ## ANDR
 ```
-Full name:
-Usage:
-Effect: 
+Full name: AND Register
+Usage: ANDR R0, R1
+Effect: R0 is and-ed by R1.
 ```
 ## YORB
 ```
-Full name:
-Usage:
-Effect: 
+Full name: (Y)OR Byte (immediate)
+Usage: YORB R0, 0xFF
+Effect: R0's lower byte is or-ed by 0xFF.
 ```
 ## YORW
 ```
-Full name:
-Usage:
-Effect: 
+Full name: (Y)OR Word (immediate)
+Usage: YORW R0, 0xFFFF
+Effect: R0's is or-ed by 0xFFFF.
 ```
 ## YORR
 ```
-Full name:
-Usage:
-Effect: 
+Full name: (Y)OR Register
+Usage: YORR R0, R1
+Effect: R0 is or-ed by R1.
 ```
 ## XORB
 ```
-Full name:
-Usage:
-Effect: 
+Full name: XOR Byte (immediate)
+Usage: XORB R0, 0xFF
+Effect: R0's lower byte is xor-ed by 0xFF.
 ```
 ## XORW
 ```
-Full name:
-Usage:
-Effect: 
+Full name: XOR Word (immediate)
+Usage: XORW R0, 0xFFFF
+Effect: R0 is xor-ed by 0xFFFF.
 ```
 ## XORR
 ```
-Full name:
-Usage:
-Effect: 
+Full name: XOR Register
+Usage: XORR R0, R1
+Effect: R0 is xor-ed by R1.
 ```
 ## NOTR
 ```
-Full name:
-Usage:
-Effect: 
+Full name: NOT Register
+Usage: NOTR R0
+Effect: Bitwise negation of R0.
 ```
 ## MULI
 ```
-Full name:
-Usage:
-Effect: 
+Full name: MULtiply by Immediate
+Usage: MULI R0, 2
+Effect: R0 is multiplied by 2.
 ```
 ## MULR
 ```
-Full name:
-Usage:
-Effect: 
+Full name: MULtiply by Register
+Usage: MULR R0, R1
+Effect: R0 is multiplied by R1.
 ```
 ## DIVI
 ```
-Full name:
-Usage:
-Effect: 
+Full name: DIVide by Immediate
+Usage: DIVI R0, 2
+Effect: R0 is divided by 2. The remainder is not stored.
 ```
 ## DIVR
 ```
-Full name:
-Usage:
-Effect: 
+Full name: DIVide by Register 
+Usage: DIVR R0, R1
+Effect: R0 is divided by R1. The remainder is not stored.
 ```
 ## SHLI
 ```
-Full name:
-Usage:
-Effect: 
+Full name: SHift Left by Immediate
+Usage: SHLI R0, 2
+Effect: Effect: R0 is shifted 2 bits to the left.
 ```
 ## SHLR
 ```
-Full name:
-Usage:
-Effect: 
+Full name: SHift Left by Register
+Usage: SHLR R0, R1
+Effect: R0 is shifted R1 bits to the left.
 ```
 ## SHRI
 ```
-Full name:
-Usage:
-Effect: 
+Full name: SHift Right by Immediate
+Usage: SHRI R0, 2
+Effect: Effect: R0 is shifted 2 bits to the right.
 ```
 ## SHRR
 ```
-Full name:
-Usage:
-Effect: 
+Full name: SHift Right by Register
+Usage: SHRR R0, R1
+Effect: R0 is shifted R1 bits to the right.
 ```
 ## PUSH
 ```
-Full name:
-Usage:
-Effect: 
+Full name: PUSH
+Usage: PUSH R1
+Effect: Pushes R1 on top of the stack.
 ```
 ## POOP
 ```
-Full name:
-Usage:
-Effect: 
+Full name: POP (+ 1 free 'O')
+Usage: POOP R1
+Effect: Retrieves the element on top of the stack and puts it in R1.
 ```
 ## CMPB
 ```
-Full name:
-Usage:
-Effect: 
+Full name: CoMPare register to Byte
+Usage: CMPB R0, 0xff
+Effect: Compares R0 to 0xFF (R0's lower byte) and sets the ZF and CF flags.
 ```
 ## CMPW
 ```
-Full name:
-Usage:
-Effect: 
+Full name: CoMPare register to Word
+Usage: CMPW R0, 0xffff
+Effect: Compares R0 to 0xFFFF and sets the ZF and CF flags.
 ```
 ## CMPR
 ```
-Full name:
-Usage:
-Effect: 
+Full name: CoMPare register to Register
+Usage: CMPR R0, R1
+Effect: Compares R0 to R1 and sets the ZF and CF flags.
 ```
 ## JMPI
 ```
@@ -320,7 +347,7 @@ Effect: Does nothing for an instruction
 ```
 Full name: GeRMaNo
 Usage: GRMN
-Effect: Sets every register (excluding IP and RP) to GG
+Effect: Sets every register (excluding IP and RP) to GG (0x4747)
 ```
 ## DEBG
 ```
@@ -331,3 +358,4 @@ Effect: Prints the status of every register and the flags
 
 [Instruction]: ./res/instruction.png
 [Structure]: ./res/structure.png
+[Functions]: ./res/functions.png

README.md

@@ -11,7 +11,7 @@ The design and the implementation behind Pasticciotto are not state-of-the-art b
 I do not want to spoil the challenge for those that haven't completed it yet. Check out some write-up online!
 
 # Instruction set
-Check out the file [INSTRUCTION_SET.MD](IS) to understand how the VM works and which operations it can do! Watch out for some spoilers if you haven't completed the challenge though!
+Check out the file [IMPLEMENTATION.MD](IMPL) to understand how the VM works and which operations it can do! Watch out for some spoilers if you haven't completed the challenge though!
 
 # Why "Pasticciotto"?
 In Italian, "Pasticciotto" has two meanings! 
@@ -44,4 +44,4 @@ OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 DEALINGS IN THE SOFTWARE.
 ```
 [Pasticciotto]: ./res/pasticciotto.png
-[IS]: ./INSTRUCTION_SET.md
+[IMPL]: ./IMPLEMENTATION.md