Opcode encryption in assembler
This commit is contained in:
Giulio De Pasquale
parent
e1f984c72d
commit
1431f6e104
@ -2,33 +2,38 @@ import sys
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import re
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import struct
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import IPython
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import copy
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class InvalidRegisterException(Exception):
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class AssemblerException(Exception):
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pass
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class InvalidRegister(AssemblerException):
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def __init__(self, register):
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super().__init__("Invalid register: {}".format(register))
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class InvalidOperationException(Exception):
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class InvalidOperation(AssemblerException):
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def __init__(self, operation):
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super().__init__("Invalid operation: {}".format(operation))
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class ExpectedImmediateException(Exception):
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class ExpectedImmediate(AssemblerException):
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def __init__(self, value):
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super().__init__("Expected immediate, got {}".format(value))
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class ExpectedRegisterException(Exception):
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class ExpectedRegister(AssemblerException):
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def __init__(self, value):
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super().__init__("Expected register, got {}".format(value))
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class IPOverwriteException(Exception):
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class IPOverwrite(AssemblerException):
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def __init__(self, instruction=None):
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if instruction:
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@ -37,17 +42,23 @@ class IPOverwriteException(Exception):
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super().__init__("IP can't be overwritten.")
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class InvalidValueException(Exception):
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class InvalidValue(AssemblerException):
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def __init__(self, instruction):
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super().__init__("Invalid value while assembling: {}".format(instruction))
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rol = lambda val, r_bits, max_bits: \
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(val << r_bits%max_bits) & (2**max_bits-1) | \
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((val & (2**max_bits-1)) >> (max_bits-(r_bits%max_bits)))
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class VMAssembler:
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assembled_code = bytearray()
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def __init__(self, key):
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self.assembled_code = bytearray()
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self.define_ops(key)
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def parse(self, instruction):
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action = getattr(self, "{}".format(instruction.opcode.name))
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action = getattr(self, "op_{}".format(instruction.opcode.name))
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action(instruction)
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def process_code_line(self, line):
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@ -64,20 +75,15 @@ class VMAssembler:
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opcode = instruction.opcode
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reg = instruction.args[0]
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imm = instruction.args[1]
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print(instruction)
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if reg.name != "ip":
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if imm.isimm():
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if reg.isreg():
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if opcode.uint8() and reg.uint8() and imm.uint16():
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if reg.name == "ip":
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raise IPOverwrite(instruction)
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if not imm.isimm():
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raise ExpectedImmediate(imm)
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if not reg.isreg():
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raise ExpectedRegister(reg)
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if not opcode.uint8() or not reg.uint8() or not imm.uint16():
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raise InvalidValue(instruction)
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self.assembled_code += opcode.uint8() + reg.uint8() + imm.uint16()
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else:
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raise InvalidValueException(instruction)
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else:
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raise ExpectedRegisterException(reg)
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else:
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raise ExpectedImmediateException(imm)
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else:
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raise IPOverwriteException(instruction)
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return
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def reg2reg(self, instruction):
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@ -90,47 +96,55 @@ class VMAssembler:
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opcode = instruction.opcode
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imm = instruction.args[0]
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reg = instruction.args[1]
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print(instruction)
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if reg.name != "ip":
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if imm.isimm():
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if reg.isreg():
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if opcode.uint8() and reg.uint8() and imm.uint16():
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if reg.name == "ip":
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raise IPOverwrite(instruction)
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if not imm.isimm():
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raise ExpectedImmediate(imm)
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if not reg.isreg():
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raise ExpectedRegister(reg)
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if not opcode.uint8() or not reg.uint8() or not imm.uint16():
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raise InvalidValue(instruction)
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self.assembled_code += opcode.uint8() + imm.uint16() + reg.uint8()
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else:
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raise InvalidValueException(instruction)
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else:
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raise ExpectedRegisterException(reg)
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else:
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raise ExpectedImmediateException(imm)
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else:
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raise IPOverwriteException(instruction)
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return
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def imm(self, instruction):
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return
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def movi(self, instruction):
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def op_movi(self, instruction):
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self.imm2reg(instruction)
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def movr(self, instruction):
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def op_movr(self, instruction):
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self.reg2reg(instruction)
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def getm(self, instruction):
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def op_load(self, instruction):
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self.imm2reg(instruction)
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def putm(self, instruction):
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def op_stor(self, instruction):
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self.reg2imm(instruction)
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def addi(self, instruction):
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def op_addi(self, instruction):
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self.imm2reg(instruction)
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def define_ops(self, key):
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key_ba = bytearray(key, 'utf-8')
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olds = copy.deepcopy(ops)
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for b in key_ba:
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for op_com in ops:
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if b % 2:
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op_com.set_value(rol(b ^ op_com.value, b % 8, 8))
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else:
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op_com.set_value(rol(b ^ op_com.value, (b + 1) % 8, 8))
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for i in ops:
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for j in ops:
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j.set_value(rol(j.value, i.value % 8, 8))
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for o, n in zip(olds, ops):
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print("{} : {}->{}".format(o.name, hex(o.value), hex(n.value)))
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class VMComponent:
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"""
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Represents a register, operation or an immediate the VM recognizes
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"""
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name = ""
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value = ""
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def __init__(self, name, value):
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self.name = name.casefold()
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@ -139,6 +153,12 @@ class VMComponent:
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def __repr__(self):
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return "{}".format(self.name)
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def set_name(self, name):
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self.name = name
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def set_value(self, value):
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self.value = value
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def uint8(self):
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numre = re.compile("^[0-9]+$")
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if isinstance(self.value, int):
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@ -203,8 +223,8 @@ class VMInstruction:
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op_names = ["MOVI",
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"MOVR",
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"GETM",
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"PUTM",
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"LOAD",
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"STOR",
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"ADDI",
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"ADDR",
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"SUBI",
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@ -220,8 +240,10 @@ op_names = ["MOVI",
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"PUSH",
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"POOP",
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"CALL",
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"HALT",
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"NOPE"]
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"SHIT",
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"NOPE",
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"GERM"]
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reg_names = ["R0", "R1", "R2", "R3", "S0", "S1", "S2", "S3", "IP", "BP", "SP"]
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section_names = ["DATA:", "CODE:", "STACK:"]
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section_flags = {s.casefold(): i + 1 for i, s in enumerate(section_names)}
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@ -230,7 +252,6 @@ regs = [VMComponent(s.casefold(), i) for i, s in enumerate(reg_names)]
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def value_from_list(fromlist, name):
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global ops, regs
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"""
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returns a tuple (name, value) from a list of VMComponents
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"""
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@ -238,9 +259,9 @@ def value_from_list(fromlist, name):
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if el.name == name:
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return (el.name, el.value)
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if fromlist == ops:
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raise InvalidOperationException(name)
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raise InvalidOperation(name)
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elif fromlist == regs:
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raise InvalidRegisterException(name)
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raise InvalidRegister(name)
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def name_from_list(fromlist, value):
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@ -259,12 +280,12 @@ def assemble_data(line):
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def main():
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if len(sys.argv) < 3:
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print("Usage: {} file_to_assemble output".format(sys.argv[0]))
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if len(sys.argv) < 4:
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print("Usage: {} opcodes_key file_to_assemble output".format(sys.argv[0]))
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return
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vma = VMAssembler()
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with open(sys.argv[1], 'r') as f:
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gen = (line.casefold().strip("\n") for line in f if line != "\n")
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vma = VMAssembler(sys.argv[1])
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with open(sys.argv[2], 'r') as f:
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gen = (line.casefold().strip() for line in f if line != "\n")
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flag = None
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for line in gen:
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@ -278,7 +299,7 @@ def main():
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if not flag:
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sys.stderr.write(
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"Nothing was assembled! Did you use the section delimiters?\n")
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with open(sys.argv[2], 'wb') as f:
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with open(sys.argv[3], 'wb') as f:
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f.write(vma.assembled_code)
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if __name__ == '__main__':
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