diff --git a/vm/vm.cpp b/vm/vm.cpp
index 105b844..6634a1e 100644
--- a/vm/vm.cpp
+++ b/vm/vm.cpp
@@ -159,8 +159,9 @@ bool VM::execMOVI(void) {
   dst = as.code[regs[IP] + 1];
   imm = *((uint16_t *)&as.code[regs[IP] + 2]);
   DBG_INFO(("MOVI %s, 0x%x\n", getRegName(dst), imm));
-  if (!dstRegCheck(dst))
+  if (!dstRegCheck(dst)) {
     return false;
+  }
   regs[dst] = imm;
   return true;
 }
@@ -175,9 +176,7 @@ bool VM::execMOVR(void) {
   dst = as.code[regs[IP] + 1] >> 4;
   src = as.code[regs[IP] + 1] & 0b00001111;
   DBG_INFO(("MOVR %s, %s\n", getRegName(dst), getRegName(src)));
-  if (dst == IP || src == IP || dst == SP || src == SP || dst == RP ||
-      src == RP) {
-    DBG_ERROR(("MOVR: Invalid register!\n"));
+  if (!srcDstRegCheck(src, dst)) {
     return false;
   }
   regs[dst] = regs[src];
@@ -193,6 +192,9 @@ bool VM::execLODI(void) {
   dst = as.code[regs[IP] + 1];
   src = *((uint16_t *)&as.code[regs[IP] + 2]);
   DBG_INFO(("LODI %s, 0x%x\n", getRegName(dst), src));
+  if (!dstRegCheck(dst)) {
+    return false;
+  }
   regs[dst] = *((uint16_t *)&as.data[src]);
   return true;
 }
@@ -206,6 +208,9 @@ bool VM::execLODR(void) {
   dst = as.code[regs[IP] + 1] >> 4;
   src = as.code[regs[IP] + 1] & 0b00001111;
   DBG_INFO(("LODR %s, %s\n", getRegName(dst), getRegName(src)));
+  if (!srcDstRegCheck(src, dst)) {
+    return false;
+  }
   regs[dst] = *((uint16_t *)&as.data[regs[src]]);
   return true;
 }
@@ -218,6 +223,9 @@ bool VM::execSTRI(void) {
   dst = *((uint16_t *)&as.code[regs[IP] + 1]);
   src = as.code[regs[IP] + 3];
   DBG_INFO(("STRI 0x%x, %s\n", dst, getRegName(src)));
+  if (!dstRegCheck(dst)) {
+    return false;
+  }
   *((uint16_t *)&as.data[dst]) = regs[src];
   return true;
 }
@@ -232,6 +240,9 @@ bool VM::execSTRR(void) {
   dst = as.code[regs[IP] + 1] >> 4;
   src = as.code[regs[IP] + 1] & 0b00001111;
   DBG_INFO(("STRR %s, %s\n", getRegName(dst), getRegName(src)));
+  if (!srcDstRegCheck(src, dst)) {
+    return false;
+  }
   *((uint16_t *)&as.data[regs[dst]]) = regs[src];
   return true;
 }
@@ -246,6 +257,9 @@ bool VM::execADDI(void) {
   dst = as.code[regs[IP] + 1];
   src = *((uint16_t *)&as.code[regs[IP] + 2]);
   DBG_INFO(("ADDI %s, 0x%x\n", getRegName(dst), src));
+  if (!dstRegCheck(dst)) {
+    return false;
+  }
   regs[dst] += src;
   return true;
 }
@@ -260,6 +274,9 @@ bool VM::execADDR(void) {
   dst = as.code[regs[IP] + 1] >> 4;
   src = as.code[regs[IP] + 1] & 0b00001111;
   DBG_INFO(("ADDR %s, 0x%x\n", getRegName(dst), src));
+  if (!srcDstRegCheck(src, dst)) {
+    return false;
+  }
   regs[dst] += regs[src];
   return true;
 }
@@ -274,6 +291,9 @@ bool VM::execSUBI(void) {
   dst = as.code[regs[IP] + 1];
   src = *((uint16_t *)&as.code[regs[IP] + 2]);
   DBG_INFO(("SUBI %s, 0x%x\n", getRegName(dst), src));
+  if (!dstRegCheck(dst)) {
+    return false;
+  }
   regs[dst] -= src;
   return true;
 }
@@ -287,6 +307,9 @@ bool VM::execSUBR(void) {
   dst = as.code[regs[IP] + 1] >> 4;
   src = as.code[regs[IP] + 1] & 0b00001111;
   DBG_INFO(("SUBR %s, 0x%x\n", getRegName(dst), src));
+  if (!srcDstRegCheck(src, dst)) {
+    return false;
+  }
   regs[dst] -= regs[src];
   return true;
 }
@@ -300,6 +323,9 @@ bool VM::execANDB(void) {
   dst = as.code[regs[IP] + 1];
   src = as.code[regs[IP] + 2];
   DBG_INFO(("ANDB %s, 0x%x\n", getRegName(dst), src));
+  if (!dstRegCheck(dst)) {
+    return false;
+  }
   regs[dst] &= src;
   return true;
 }
@@ -313,6 +339,9 @@ bool VM::execANDW(void) {
   dst = as.code[regs[IP] + 1];
   src = *((uint16_t *)&as.code[regs[IP] + 2]);
   DBG_INFO(("XORW %s, 0x%x\n", getRegName(dst), src));
+  if (!dstRegCheck(dst)) {
+    return false;
+  }
   regs[dst] &= src;
   return true;
 }
@@ -326,6 +355,9 @@ bool VM::execANDR(void) {
   dst = as.code[regs[IP] + 1] >> 4;
   src = as.code[regs[IP] + 1] & 0b00001111;
   DBG_INFO(("ANDR %s, 0x%x\n", getRegName(dst), src));
+  if (!srcDstRegCheck(src, dst)) {
+    return false;
+  }
   regs[dst] &= regs[src];
   return true;
 }
@@ -339,6 +371,9 @@ bool VM::execYORB(void) {
   dst = as.code[regs[IP] + 1];
   src = as.code[regs[IP] + 2];
   DBG_INFO(("YORB %s, 0x%x\n", getRegName(dst), src));
+  if (!dstRegCheck(dst)) {
+    return false;
+  }
   regs[dst] |= src;
   return true;
 }
@@ -352,6 +387,9 @@ bool VM::execYORW(void) {
   dst = as.code[regs[IP] + 1];
   src = *((uint16_t *)&as.code[regs[IP] + 2]);
   DBG_INFO(("XORW %s, 0x%x\n", getRegName(dst), src));
+  if (!dstRegCheck(dst)) {
+    return false;
+  }
   regs[dst] |= src;
   return true;
 }
@@ -365,6 +403,9 @@ bool VM::execYORR(void) {
   dst = as.code[regs[IP] + 1] >> 4;
   src = as.code[regs[IP] + 1] & 0b00001111;
   DBG_INFO(("XORR %s, 0x%x\n", getRegName(dst), src));
+  if (!srcDstRegCheck(src, dst)) {
+    return false;
+  }
   regs[dst] |= regs[src];
   return true;
 }
@@ -378,6 +419,9 @@ bool VM::execXORB(void) {
   dst = as.code[regs[IP] + 1];
   src = as.code[regs[IP] + 2];
   DBG_INFO(("XORB %s, 0x%x\n", getRegName(dst), src));
+  if (!dstRegCheck(dst)) {
+    return false;
+  }
   regs[dst] ^= src;
   return true;
 }
@@ -391,6 +435,9 @@ bool VM::execXORW(void) {
   dst = as.code[regs[IP] + 1];
   src = *((uint16_t *)&as.code[regs[IP] + 2]);
   DBG_INFO(("XORW %s, 0x%x\n", getRegName(dst), src));
+  if (!dstRegCheck(dst)) {
+    return false;
+  }
   regs[dst] ^= src;
   return true;
 }
@@ -404,6 +451,9 @@ bool VM::execXORR(void) {
   dst = as.code[regs[IP] + 1] >> 4;
   src = as.code[regs[IP] + 1] & 0b00001111;
   DBG_INFO(("XORR %s, 0x%x\n", getRegName(dst), src));
+  if (!srcDstRegCheck(src, dst)) {
+    return false;
+  }
   regs[dst] ^= regs[src];
   return true;
 }
@@ -417,6 +467,9 @@ bool VM::execNOTR(void) {
   dst = as.code[regs[IP] + 1] >> 4;
   src = as.code[regs[IP] + 1] & 0b00001111;
   DBG_INFO(("NOTR %s, 0x%x\n", getRegName(dst), src));
+  if (!srcDstRegCheck(src, dst)) {
+    return false;
+  }
   regs[dst] = ~regs[src];
   return true;
 }
@@ -430,6 +483,9 @@ bool VM::execMULI(void) {
   dst = as.code[regs[IP] + 1];
   src = *((uint16_t *)&as.code[regs[IP] + 2]);
   DBG_INFO(("SUBI %s, 0x%x\n", getRegName(dst), src));
+  if (!dstRegCheck(dst)) {
+    return false;
+  }
   regs[dst] *= src;
   return true;
 }
@@ -443,6 +499,9 @@ bool VM::execMULR(void) {
   dst = as.code[regs[IP] + 1] >> 4;
   src = as.code[regs[IP] + 1] & 0b00001111;
   DBG_INFO(("MULR %s, 0x%x\n", getRegName(dst), src));
+  if (!srcDstRegCheck(src, dst)) {
+    return false;
+  }
   regs[dst] *= regs[src];
   return true;
 }
@@ -456,6 +515,9 @@ bool VM::execDIVI(void) {
   dst = as.code[regs[IP] + 1];
   src = *((uint16_t *)&as.code[regs[IP] + 2]);
   DBG_INFO(("DIVI %s, 0x%x\n", getRegName(dst), src));
+  if (!dstRegCheck(dst)) {
+    return false;
+  }
   regs[dst] /= src;
   return true;
 }
@@ -469,6 +531,9 @@ bool VM::execDIVR(void) {
   dst = as.code[regs[IP] + 1] >> 4;
   src = as.code[regs[IP] + 1] & 0b00001111;
   DBG_INFO(("DIVR %s, 0x%x\n", getRegName(dst), src));
+  if (!srcDstRegCheck(src, dst)) {
+    return false;
+  }
   regs[dst] /= regs[src];
   return true;
 }
@@ -482,6 +547,9 @@ bool VM::execSHLI(void) {
   dst = as.code[regs[IP] + 1];
   src = *((uint16_t *)&as.code[regs[IP] + 2]);
   DBG_INFO(("SHLI %s, 0x%x\n", getRegName(dst), src));
+  if (!dstRegCheck(dst)) {
+    return false;
+  }
   regs[dst] = regs[dst] << src;
   return true;
 }
@@ -495,6 +563,9 @@ bool VM::execSHLR(void) {
   dst = as.code[regs[IP] + 1] >> 4;
   src = as.code[regs[IP] + 1] & 0b00001111;
   DBG_INFO(("SHLR %s, 0x%x\n", getRegName(dst), src));
+  if (!srcDstRegCheck(src, dst)) {
+    return false;
+  }
   regs[dst] = regs[dst] << regs[src];
   return true;
 }
@@ -508,6 +579,9 @@ bool VM::execSHRI(void) {
   dst = as.code[regs[IP] + 1];
   src = *((uint16_t *)&as.code[regs[IP] + 2]);
   DBG_INFO(("SHRI %s, 0x%x\n", getRegName(dst), src));
+  if (!dstRegCheck(dst)) {
+    return false;
+  }
   regs[dst] = regs[dst] >> src;
   return true;
 }
@@ -521,6 +595,9 @@ bool VM::execSHRR(void) {
   dst = as.code[regs[IP] + 1] >> 4;
   src = as.code[regs[IP] + 1] & 0b00001111;
   DBG_INFO(("SHRR %s, 0x%x\n", getRegName(dst), src));
+  if (!srcDstRegCheck(src, dst)) {
+    return false;
+  }
   regs[dst] = regs[dst] >> regs[src];
   return true;
 }